METHOD FOR FORMING CONTACT HOLE

摘要

The wiring resistance itself and the variation of the wiring resistance in the same lot of semiconductor devices having a multilevel interconnection structure where at least the lower wiring layer is an aluminum wiring layer are reduced. Contact holes (31, 51) are formed in interlayer insulating layers (3, 5) of wiring layers (1, 2, 4) in two steps of dry etching. In the first etching step, CF4, CHF3, Ar, and N2 are supplied into an etching chamber. In the second etching step, CF4, CHF3, and Ar are supplied into the etching chamber.