| 摘要 |
PURPOSE: A circuit for generating addresses in a semiconductor memory device is provided to generate read/write addresses in the normal/burst modes of the semiconductor memory device having read/write function after different cycles. CONSTITUTION: A shift register(46) shifts output signals(AAB(n,...3)) of a multiplexor(42) for n cycles in response to a control signal(PWRITE). A multiplexor(44) outputs the output signal of the multiplexor in response to a read control signal(PRD). A multiplexor(48) outputs the output signal of the shift register in response to a write control signal(PWE). Then, a latch(50) latches the signal outputted from one of the multiplexors(44,48). A shift register(64) shifts the output signal of a counter(60) in response to the write control signal. A multiplexor(66) outputs the output signal of the shift register(64) in response to the write control signal. A latch(68) latches the signal outputted from multiplexors(56,62,66). Therefore, a circuit generating addresses separates the generating passages of read/write addresses in case of the formation of normal/burst addresses. Thus, the circuit is applied to a semiconductor memory device having reading/writing data after different cycles.
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