| 摘要 |
PURPOSE: A Phase Locked Loop(PLL) using synchronous detection circuit is provided to shorten lock-in time and enhance noise characteristics with reduced chip area. CONSTITUTION: A PLL using synchronous detection circuit comprises a phase frequency detector(10), a synchronous detection circuit(20), a charge pump(30), first and second low pass filters(LPFL,LPFH), first and second transmission gates(TG1,TG2), a capacitor(C) and a voltage control oscillator(40). The phase frequency detector(10) detects the phase of an input signal(IN) to output UP/DOWN signals(UP,DN) for chasing frequency. The synchronous detection circuit(20) detects whether the PLL is synchronized using the UP/DOWN signals. The charge pump(30) pumps the UP/DOWN signals. The low pass filters(LPFL,LPFH) receives the output of the pump(30). The transmission gates(TG1,TG2) selectively switches the outputs of the filters(LPFL,LPFH).
|
