| 摘要 |
PURPOSE: An Add-Compare Select(ACS) operational circuit of viterbi decoder is provided to maintain the minimum value of error accumulated values to the value less than a constant value and compensate an overflow. CONSTITUTION: An ACS operational circuit of viterbi decoder comprises a first multiplexor(MUX1), first and second subtracters(411,412), first and second adders(413,414), a comparator(415) and a second multiplexor(MUX2). The first multiplexor(MUX1) outputs a constant value or 0 value. The subtracters(411,412) subtract the output value of the first multiplexor from a pass matrix. The adders(413,414) add a branch matrix to the values subtracted in the subtracters. The comparator(415) compares two values output from the adders to output a select signal for informing a less value among the two values. The second multiplexor(MUX2) selects the less value of the two values to output the less value as a new pass matrix.
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