| 摘要 |
PURPOSE: A high speed interpolator of digital decoder is provided to respond to high speed system clock by storing the output from a ROM. CONSTITUTION: A high speed interpolator of digital decoder includes an address generator, a memory, a delay, a multiplier, and an adder. The interpolator recontrols the sampled signal in response to a symbol timing. The address generator receives decimal values between 0 and 1 and shifts down the number to generate a memory address. The memory stores a result of prior process, and receives the memory address from the address generator to read the address. The delay delays the input data for a predetermined period of time and outputs the delayed input. The multiplier multiplies the result of manipulation from the memory by the delayed input data from the. The adder adds the multiplied signal from the multiplier to generate an interpolant.
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