| 摘要 |
PURPOSE: A memory access system is provided to have an identical speed to a dual port RAM(DPRAM) memory access system, by using a one-directional accessible memory device instead of a bidirectional accessible DPRAM. CONSTITUTION: A memory unit(100) is one-directional accessible. A first buffer unit(400) temporarily latches a first memory control signal accessing the memory unit(100) from a first processor(20). A second buffer unit(500) temporarily latches a second memory control signal accessing the memory unit(100) from a second processor(30). A first memory controller(200) responds to a first memory access signal from the first processor(20), provides a first buffer enable signal to output the first memory control signal, and maintains the first memory control signal until the memory access of the second processor(30) is completed, when a second memory access signal from the second processor(30) is prior to the first memory access signal. A second memory controller(300) responds to the second memory access signal from the second processor(30), provides a second buffer enable signal to output the second memory control signal, and maintains the second memory control signal until the memory access of the first processor(20) is completed, when the first memory access signal is prior to the second memory access signal.
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