发明名称 MULTI-PROCESSOR SYSTEM
摘要 <p>PROBLEM TO BE SOLVED: To attain high speed lock processing by using a memory mapped communication register without changing any processor in a multi-processor system. SOLUTION: This multi-processor system is provided with communication register modules 400-402 corresponding to processors 10-12 one to one, and a lock processing test operation is operated to the corresponding communication register modules, and a lock value set operation and an unlock operation are operated through an inter-communication module bus to all the communication modules by executing simultaneous writing control.</p>
申请公布号 JP2000187652(A) 申请公布日期 2000.07.04
申请号 JP19980366340 申请日期 1998.12.24
申请人 HITACHI LTD 发明人 TAMAOKI YOSHIKO;SUKEGAWA NAONOBU;FUKAGAWA SHOICHI
分类号 G06F15/17;G06F9/46;G06F9/52;G06F15/16;G06F15/177;(IPC1-7):G06F15/177 主分类号 G06F15/17
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