发明名称 |
Stacked capacitor memory cell and method of manufacture |
摘要 |
A DRAM memory cell structure of a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) and a stacked capacitor and a method for forming same facilitates low resistance contact between the source/drain of the transistor and a lower electrode of the capacitor. The method in its preferred embodiment uses platinum for the bottom electrode of the capacitor without the need for a diffusion barrier between it and a doped polysilicon plug used to contact the MOSFET. To this end, the formation of the contact is after the deposition of the high dielectric material, such as barium strontium titanate, used to form the dielectric of the capacitor. Also the bottom electrode of the capacitor is partially offset with respect to the polysilicon plug.
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申请公布号 |
US6083788(A) |
申请公布日期 |
2000.07.04 |
申请号 |
US19990277669 |
申请日期 |
1999.03.26 |
申请人 |
INFINEON TECHNOLOGIES NORTH AMERICA CORP. |
发明人 |
LIAN, JENNY;KUNKEL, GERHARD |
分类号 |
H01L27/105;H01L21/02;H01L21/768;H01L21/8242;H01L21/8246;(IPC1-7):H01L21/824 |
主分类号 |
H01L27/105 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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