| 摘要 |
An electrostatic discharge protective circuit including a semiconductor substrate, an input/output pad formed on the semiconductor substrate, a PMOS transistor formed on the semiconductor substrate and having a drain connected to the input/output pad, a first n+ diffusion layer formed in the semiconductor substrate and separated from the drain of the PMOS transistor at a predetermined interval while being connected to a Vcc terminal, a deep n+ diffusion layer formed between the drain of the PMOS transistor and the first n+ diffusion layer, an NMOS transistor formed on the semiconductor substrate and having a drain connected to the input/output pad, and second n+ diffusion layers formed around the NMOS transistor in the semiconductor substrate and connected to a Vss terminal.
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