| 摘要 |
PROBLEM TO BE SOLVED: To make a low voltage interface and a low electric power consumption compatible by decreasing a clock signal line in the load and the electric power consumption. SOLUTION: When a clock signal CK is 'H' and an input pulse signal in (a 1st control signal) is 'H', n type transistors M15, 16 are turned on and an output node/OUT becomes the ground level. Then, p type transistor M12 is turned on and the output node OUT becomes Vcc level (16 V). Thus, a latch circuit LAT operates as a level shifter circuit when the 1st and 2nd control signals and the clock signal CK are 'H', and otherwise, it operates as a level holding circuit. Therefore, the shift register circuit composed of the latch circuit LAT functions as a low voltage interface and also the clock signal CK input is interrupted when the latch circuit LAT is inactive, and load reduction in the clock signal line and decrease in power consumption are achieved. |
