High speed flat-cell mask ROM structure with select lines

摘要

A flat-cell ROM array reduces the number of transistors utilized to read a memory cell, allows for the layout of straight metal lines, while sharing the metal lines between even and odd cells, and achieves very high density and high performance. Parallel buried diffusion regions are implanted in the substrate. A gate oxide is laid over the substrate. A plurality of polysilicon word lines are laid over the gate oxide perpendicular to the buried diffusion regions, so that the areas between respective pairs of buried diffusion regions and under the polysilicon word lines, form columns of flat cell field effect transistors. An insulating layer is laid over the polysilicon word lines and a plurality of metal bit lines and virtual ground lines are formed. These metal lines are shared by even and odd columns of field effect transistors. Access to metal lines is made through a plurality of block select transistors connected to every other buried diffusion bit line. The alternate buried diffusion bit lines are connected to every other buried diffusion region by odd and even select transistors.