| 摘要 |
PROBLEM TO BE SOLVED: To enhance a signal processing speed by reducing an arithmetic quantity required for demodulation processing without deteriorating an error rate characteristic. SOLUTION: Level detectors 112-115 detect a reception level of an input signal subject to DFT processing by a DFT circuit 101, a selector 102 extracts a carrier whose reception level is lowest from the result of the level detectors 112-115, the detection processing of this carrier is assigned to a synchronization detector 106 and the detection processing of the other three carriers is assigned to delay detectors 103-105.
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