发明名称 |
Methods for configuring fpga's having variable grain blocks and shared logic forproviding time-shared access to interconnect resources |
摘要 |
A Variable Grain Architecture (VGA) includes a shared output component (SOC) that may be used for outputting different signals onto a shared longline within an FPGA. Plural VGB's make shared use of the SOC to out respective function signals to the shared longline. |
申请公布号 |
AU2190800(A) |
申请公布日期 |
2000.07.03 |
申请号 |
AU20000021908 |
申请日期 |
1999.12.15 |
申请人 |
LATTICE SEMICONDUCTOR CORPORATION |
发明人 |
OM P. AGRAWAL;BRADLEY A. SHARPE-GEISLER;HERMAN M. CHANG;BAI NGUYEN;GIAP H. TRAN |
分类号 |
H03K19/173;H03K19/177 |
主分类号 |
H03K19/173 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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