| 摘要 |
PROBLEM TO BE SOLVED: To obtain a logical synthesizing device by which the mutual timings of signals related to tri-state buses are optimized and the buses are suitably created by changing the cell of standard circuit information to satisfy the ideal assert period condition of tri-state buffers, creating timing circuit information and outputting it as circuit configuration information. SOLUTION: CPU 1 executes a change processing to satisfy the ideal asset period condition 11 of the tri-state buffers 16 and 17 and the ideal assert period condition 12 of data latching half latches 20 and 21 for latching the outputs of the tri-state buffers 16 and 17 together with the ideal clock signal condition 10 of synchronizing flip-flops 24-31. Therefore, the ideal assert periods of the tri-state buffers 16 and 17 are designated as an individual period so that an output collision in the tri-state buses 15 connected to the output sides of the plural tri-state buffers 16 and 17 is evaded.
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