发明名称 Sticky bit value predicting circuit
摘要 <p>A sticky bit value of the product of mantissas X and Y is predicted by a circuit that comprises a bit pattern generation circuit 25A that generates a bit pattern B, based on a trailing zero bit pattern of the multiplier Y, having all values of the sticky bit S corresponding to any number C of the trailing Os of the multiplicand X; a priority encoder 21 for providing the number C depending on X; and a sticky bit selection circuit 26A for selecting one bit in the bit pattern B as a value of the sticky bit S depending on the value C. &lt;IMAGE&gt;</p>
申请公布号 EP1014260(A1) 申请公布日期 2000.06.28
申请号 EP19990204495 申请日期 1999.12.24
申请人 FUJITSU LIMITED 发明人 TSUJI, MASAYUKI
分类号 G06F7/38;G06F7/487;G06F7/52;(IPC1-7):G06F7/52 主分类号 G06F7/38
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