| 摘要 |
Output stage with self calibrating slew rate control. An output stage comprising a first (1) and a second (2) supply terminal for receiving a supply voltage (SV); a pre-drive circuit (PDS) coupled to an input terminal (IP) for receiving an input signal (Vi), the pre-drive circuit (PDS) comprising a series transistor (TS) with a control electrode (TSg) for receiving a control voltage (Vcntrl) for controlling a maximum current from an output (PDSOUT) of the pre-drive circuit (PDS), and a capacitor (C) for retaining the control voltage (Vcntrl); an output-drive circuit (ODS) for delivering an output signal (Vo) at an output terminal (OP) in response to the input signal (Vi); and a control circuit (CC) for delivering the control voltage (Vcntrl). The output stage further comprises a control circuit (CC) which is coupled between the output terminal (OP) and the control electrode (TSg). The pre-drive circuit (PDS) and the output-drive circuit (ODS) together form a non-inverting output stage. If the slew rate of the output signal (Vo) is too large it will gradually be reduced by adapting the control voltage (Vcntrl) The control circuit CC, the pre-drive circuit (PDS), and the output-drive circuit (ODS) together form a clocked feedback loop in order to automatically calibrate the slew rate of the output signal (Vo) during a few clock cycles.
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