发明名称 |
Method for preventing micromasking in shallow trench isolation process etching |
摘要 |
An isolation structure on an integrated circuit is formed using a shallow trench isolation process. A layer of buffer oxide is formed on a substrate. A layer of nitride is formed on the layer of buffer oxide. The layer of nitride and the layer of buffer oxide are patterned to form a trench area. The substrate including the trench area is subjected to a plasma comprising H2O vapor, and a gaseous fluorocarbon or a fluorinated hydrocarbon gas to clean impurities on the trench area. The substrate is etched to form a trench within the trench area.
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申请公布号 |
US6080677(A) |
申请公布日期 |
2000.06.27 |
申请号 |
US19970002103 |
申请日期 |
1997.12.30 |
申请人 |
VLSI TECHNOLOGY, INC. |
发明人 |
GABRIEL, CALVIN;HARVEY, IAN ROBERT;LEARD, LINDA |
分类号 |
H01L21/28;H01L21/285;H01L21/306;H01L21/336;(IPC1-7):H01L21/76 |
主分类号 |
H01L21/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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