| 摘要 |
A pipelined computer comprises a plurality of stages. An instruction subsequent to an operation mode changing instruction is held in a predetermined stage according to a type of the operation mode changing instruction. For example, if the instruction is the one subsequent to an ICP (Instruction mode Change to Privilege) instruction, it is held in an instruction decode stage where a privilege exception is detected. If the instruction is the one subsequent to an ACS (Addressing mode Change to Secure) instruction, it is held in an address adding stage where an address computation is performed. Moreover, if the instruction is the one subsequent to an ACD (Addressing mode Change to Direct) instruction, they are held in an address translation stage where an address translation is performed. These holdings are released after the operation mode changing instruction is completed. Furthermore, if the subsequent instructions are the ones which are not affected by the operation mode changing instruction, the subsequent instruction may be controlled so as not to be held.
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