High speed interlaced analog interface

摘要

An apparatus for wide bandwidth analog to digital and digital to analog signal conversion is disclosed. An input/output stage (40) is coupled to an external analog system and includes reference voltages for calibration of the analog to digital (A/D) conversion process. A conversion stage (46), comprising a plurality of A/D converters (ADC) (48, 50) and a digital to analog converter (52), is coupled to the input/output stage and to a digital signal conditioning stage (54) which is coupled to an external digital system. Offset and gain errors in the outputs of each ADC are corrected by the application of appropriate correction parameters in the digital signal conditioning stage. The sampling intervals for each ADC are phased to allow the digital outputs of the ADCs to be interleaved and form a resulting digital data stream with a sampling rate a multiple of that of any one ADC.