| 发明名称 |
Semiconductor memory device |
| 摘要 |
In a dynamic random access memory, at a time of body-refresh operation, a bit-line potential VBL is set to a body-refresh-potential VBR, and the body-refresh-potential VBR is supplied to bit-line pairs via a bit-line precharging/equalizing circuit 111c, thereby the charge accumulated in the body of the n channel MOS transistor 72cb in a memory cell is drained to the bit-line pairs.
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| 申请公布号 |
US6081443(A) |
申请公布日期 |
2000.06.27 |
| 申请号 |
US19980222799 |
申请日期 |
1998.12.30 |
| 申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
MORISHITA, FUKASHI;TOMISHIMA, SHIGEKI;ARIMOTO, KAZUTANI |
| 分类号 |
H01L21/76;G11C11/401;G11C11/404;G11C11/406;G11C11/407;G11C11/4074;G11C11/408;H01L21/8242;H01L27/108;(IPC1-7):G11C11/24 |
主分类号 |
H01L21/76 |
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