| 摘要 |
An apparatus which receives a gapped data component of an STS-1 signal and provides therefrom an ungapped DS-3 data signal is provided and includes a FIFO (20) for receiving the data component (12) of the STS-1 signal, a measuring circuit (40) having an input clock related to the STS-1 signal and the output clock of the apparatus as inputs for effectively measuring the relative fullness of the FIFO, and a voltage controlled crystal oscillator (VCXO) (90) for receiving a control signal from the measuring circuit and for generating the output clock of the apparatus in response thereto, where data in the FIFO is taken out of the FIFO as the DS-3 signal according to the rate of the output clock. The FIFO is preferably a byte wide RAM, and the measuring circuit is comprised of two counters, an XOR gate, and a low pass filter. By feeding back the output clock to one of the counters of the measuring circuit, a closed loop system is established.
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