| 摘要 |
An over-erasure preventing device which applies, when erasing data written in a memory cell, an erasing voltage to an N-type source, and a potential difference reducing voltage to a control gate, so that the potential difference between the N-type source and control gate is reduced. This makes it possible to solve a problem involved in a conventional device in that once the memory cell has been destroyed by an over-erasure, the data read and write become impossible although the over-erasure can be remedied.
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