发明名称 Merging dummy structure representations for improved distribution of artifacts in a semiconductor layer
摘要 A method for optimally sizing dummy structures in an integrated circuit design is disclosed. Adjacent dummy structures are merged to provide a composite merged dummy structure. Each side of a first dummy structure representation is expanded in a lateral direction by a predetermined distance such that the first dummy structure representation merges with an adjacent second dummy structure representation forming the composite merged dummy structure. The composite merged dummy structure is then examined to determine if it exceeds a predetermined size. If the composite merged dummy structure exceeds the predetermined size, then the composite merged dummy structure is contracted to fit within predetermined perimeters.
申请公布号 US6081272(A) 申请公布日期 2000.06.27
申请号 US19970941599 申请日期 1997.09.30
申请人 INTEL CORPORATION 发明人 MORIMOTO, SEIICHI;DEETER, TIMOTHY L.
分类号 G06F15/00;G06F17/50;H01L21/3105;(IPC1-7):G06F15/00 主分类号 G06F15/00
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