发明名称 |
Method for forming a MOS device with self-compensating VT-implants |
摘要 |
The present invention provides a method for forming a MOS device having self-compensating threshold adjust implants and reduced junction capacitance. A semiconductor substrate of a first conductivity type is provided. A gate oxide is formed on the surface of the semiconductor substrate, and a polysilicon gate is formed on the surface of the gate oxide. A first implant of a dopant of the first conductivity type is performed so as to form self-compensating implant regions in the semiconductor substrate on opposite sides of the gate. Disposable sidewall spacers are then formed around the polysilicon gate. A second implant of a dopant of a second conductivity type is performed so as to create highly-doped source/drain regions which are self-aligned to the sidewall spacers. The substrate with self-compensating implant regions and the highly-doped source/drain regions is then subject to a rapid thermal anneal (RTA) process so as to activate the dopant in the self-compensating implant regions and the highly-doped source/drain regions. The dopant within the self-compensating regions diffuses laterally under the polysilicon gate to define pockets. Thereafter, the disposable sidewall spacers are removed. Finally, a third implant of a dopant of the second conductivity type is performed so as to create lightly-doped source/drain regions in the self-compensating implant regions on opposite sides of the gate.
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申请公布号 |
US6080630(A) |
申请公布日期 |
2000.06.27 |
申请号 |
US19990243014 |
申请日期 |
1999.02.03 |
申请人 |
ADVANCED MICRO DEVICES, INC. |
发明人 |
MILIC-STRKALJ, OGNJEN;ROUSE, RICHARD;KRIVOKAPIC, ZORAN |
分类号 |
H01L21/225;H01L21/336;H01L29/10;(IPC1-7):H01L21/336 |
主分类号 |
H01L21/225 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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