| 摘要 |
An arrangement for reducing power consumption in a flash A/D converter uses a predictor module to compute the "next" digital output value (i.e., +E,cir s+EE (n+1)) and then uses this value to regulate the number of individual comparators required to perform an accurate conversion. The predictor module is disposed as a feedback element between the converter output and the comparator array. Based upon the prediction, the module transmits a control signal to the comparator array, turning "on" and "off" subsets of the comparators forming the array. By maintaining a large number of the comparators in the "off" state (usually, only half of the comparators need to be enabled), a significant power savings can be realized.
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