| 摘要 |
PURPOSE: A latch circuit is provided to be easy to design a timing of an integrated circuit by minimizing a setup or hold time on the basis of a clock signal. CONSTITUTION: A latch circuit comprises an inverter(1), a differential amplifier part(3), a flipflop(4), and input buffers(21,22). The inverter(1) receives a clock signal(CLK) to output an inverted version of the clock signal(iCLK). The input buffers(21,22) receives an input signal(DN) to output a pair of differential input signals(DI,iDI). The differential amplifier part(3) comprises inverters(310,320), PMOS transistors(302,303,304), output buffers(331,332), and NMOS transistors(301,351-353,361-363). The PMOS transistors(302,303,304) and the NMOS transistors(352,351,362) are controlled by the clock signal(CLK), and the NMOS transistors(351,361) are controlled by the differential input signals(DI,iDI), respectively. The NMOS transistors(353,363) are controlled by the inverted version of the clock signal(iCLK). The flip flop(4) is set or reset according to output signals(S,R) from the output buffers(331,332).
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