| 摘要 |
PURPOSE: A clock signal generator for an integrated circuit is provided to make two internal clocks of a predetermined relationship be valid and invalid always. CONSTITUTION: A clock signal generator for an integrated circuit comprises a clock signal input buffer(11) which generates first and second internal clock signals(CLKM1,CLKM2) in response to first and second external clock signals(CLK1,CLK2) and consists of first and second clock signal input buffers(11,12), a power down signal input buffer(13), a latch circuit(14), first and second enable signal generators(15,16) and a gate circuit(17). The first clock signal input buffer(11) receives the first external clock signal(CLK1) to output a first clock signal(CLKSZ) of the same phase as the clock signal(CLK1). The second clock signal input buffer(12) receives the second external clock signal(CLK2) to output the second internal clock signal(CLKSZ) of the same phase as the clock signal(CLK2). The power down signal input buffer(13) receives an external power down signal(CKE) to output the main power down signal(CKEMZ) of the same phase as the signal(CKE). The latch circuit(14) latches the main power down signal(CKEMZ) at a low level of the internal clock signal(CLKSZ), and outputs the latched signal at a high level of the signal(CLKSZ). The first enable signal generator(15) receives and holds an internal power down signal(CKECZ) at a rising edge of the internal clock signal(CLKSZ), and outputs the held signal(CKECZ) as an enable signal(ENZ1)to the generator(16). The second enable signal generator(16) receives and holds the enable signal(ENZ1) at a rising edge of the internal clock signal(CLKSZ), and outputs the held signal(ENZ1) as an enable signal(ENZ2). The gate circuit(17) outputs the internal clock signal(CLKSZ) as the first clock signal(CLKM1) at a high level of the signal(ENZ1).
|
