| 摘要 |
PURPOSE: A semiconductor memory device is provided to prevent an operation mode from being switched into a test mode from a normal mode owing to an error. CONSTITUTION: A semiconductor memory device comprises a test mode activation control circuit(18) which consists of a delay circuit(30), a NOR circuit(31), NOT circuits(32,37-40), NAND circuits(33-36), PMOS transistors(41-44), latch circuits(45-48) and a reset circuit(54). The reset circuit(54) consists of NAND circuits(49,40,53), a NOT circuit(51) and a NOR circuit(52). The test mode activation control circuit(18) switches an operation mode of the memory device into a test mode according to a plurality of combination patterns of a command signal(MRS) and an address(A0x,A1x,A2z,A8x,A7z,A2x).
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