发明名称 INTEGRATED CIRCUIT LAYOUT DESIGNING DEVICE, INTEGRATED CIRCUIT LAYOUT DESIGNING METHOD AND STORAGE MEDIUM WITH ITS CONTROL PROGRAM RECORDED THEREIN
摘要 PROBLEM TO BE SOLVED: To provide an integrated circuit layout designing device capable of improving the operation frequency of an LSI. SOLUTION: A floor plan inputting/deciding means 1 inputs physical library information, connection information between groups and the size of each group and decides a floor plan. An inter-group wiring means 2 allows each inter-group wiring to pass an inter-group area according to the floor plan and performs wiring. A relay buffer inserting means 3 refers to wiring between the groups and the signal flow of the inter-group wiring and inserts a relay buffer. A logical circuit changing means 4 adds and corrects the inserted relay buffer to intra-group/inter-group logical connection information. An intra-group logical circuit arrangement wiring means 5 gives an arrangement position constraint to the inserted relay buffer, gives a wiring length constraint to wiring passing in a group and performs the arrangement and wiring of a logical circuit in the group.
申请公布号 JP2000172736(A) 申请公布日期 2000.06.23
申请号 JP19980349219 申请日期 1998.12.09
申请人 NEC CORP 发明人 GOTO TAKASHI
分类号 H01L21/82;G06F17/50;(IPC1-7):G06F17/50 主分类号 H01L21/82
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