| 摘要 |
PROBLEM TO BE SOLVED: To provide a multiplier circuit improved in operation precision, and reduced in scale, power consumption and price. SOLUTION: An n-bit (n: positive integer) multiplier shift register 4 holds an n-bit multiplier and shifts it to the LSB, bit by bit synchronously with a clock signal. An m-bit (m: positive integer) partial product part 7 ANDs the LSB of the multiplier shift register 4 and the respective bits of an m-bit multiplicand. AN addition part 10 adds the output of the partial product part 7 and the value of an (m+1)-bit multiplication register 12. The multiplication register 12 holds the output of the addition part 10. An (n-1)-bit multiplication shift register 13 receives the value of the LSB of the multiplication register 12 in series.
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