| 摘要 |
PROBLEM TO BE SOLVED: To reduce penalities of synchronization as much as possible and to enable adaptation to a high-speed network without degrading the performance by synchronizing integral-multiple output data of a synchronizing memory with a synchronizing clock different from its output synchronizing clock, and temporarily storing its output and making proper choices in specific process data properly. SOLUTION: A MAC part 502 put the physical layer and data link layer of the OSI model together into one block and output data width is 8 bits as the data boundary of Ethernet (R). An FIFO 503 performs read/write processes in synchronism with a clock of reception operation frequency. A register file part 504 is a register file of 128-bit constitution, for fetching 8 bits outputted in synchronism with the clock on the side of a network 501. A latching part 505 synchronizes 128-bit data with a system clock. A DMA part 506 receives the output of the latch part 505 as 8-bit data.
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