| 摘要 |
PROBLEM TO BE SOLVED: To exclude the limitation on that the start/end addresses of a data segment must be aligned with the width of a bus, for a data transfer device having the bus for prescribed byte width. SOLUTION: When starting data transfer, a processor sets the start address to an S-ADR 104, sets the end address to an E-ADR 105, sets the start address of a data-chained data segment to a C-ADR 116 and sets a DC-FLAG 115. A RAP 102 and a WAP 103 are initialized by the value of the S-ADR. The prefetch of data is started from the address of the WAP and when a detection circuit 107 detects the value of the WAP becomes an address more than the value of the E-ADR, prefetch is stopped. When a detection circuit 108 detects the difference between the values of the E-ADR and R-ADR becomes less than a prescribed value, the start of prefetch is loaded to another buffer device. A detection circuit 109 detects the difference between the values of the E-ADR and RAP becomes less than data width. An alignment circuit 113 merges data in two buffer devices and sends them onto the bus.
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