发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
摘要 PROBLEM TO BE SOLVED: To enable performing d-c test with less wirings, using a MOSFET having a low threshold voltage by switching a switch circuit according to a control signal and also serving it for a back vias voltage. SOLUTION: A switch circuit is switched by control signals PDP, PDN, and a p- and n-channel MOSFETs constituting a logic circuit are formed on a well region or a substrate to which a voltage corresponding to an operating voltage of the logic circuit is fed in the usual operation. In a d-c test mode or standby mode, a back bias voltage is fed to the well region of the logic circuit or the substrate so as to make the threshold voltage high, i.e., a voltage higher than the power voltage is fed to a p-channel MOSFET and a negative voltage lower than the ground potential of the circuit is fed to an n-channel MOSFET. Thus, it is possible to operate a CMOS circuit in two modes, effectively using wiring channels.
申请公布号 JP2000174139(A) 申请公布日期 2000.06.23
申请号 JP19980351011 申请日期 1998.12.10
申请人 HITACHI LTD 发明人 NAKAMURA YOSHIHIDE
分类号 H01L21/8238;H01L21/82;H01L27/092;H01L27/118;(IPC1-7):H01L21/823 主分类号 H01L21/8238
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