| 摘要 |
PROBLEM TO BE SOLVED: To solve the problem of delaying a signal line and limiting system performance by acquiring debugging data generated under the control of a coprocessor in response to a simultaneously executed coprocessor instruction by a main processor in a debugging mode. SOLUTION: In the debugging mode, different instructions are sent to the main processor and the coprocessor and the main processor acquires the debugging data generated under the control of the coprocessor in response to the simultaneously executed coprocessor instruction. Relating to this device, a main processor pipeline 16 responds to main processor instructions read from an instruction bus 18 and sends them to an instruction execution device 12 in order to execute them. A main processor instruction scanning chain 20 is provided in an instruction line and the instructions are inserted to an instruction pipeline 16 when debugging is operated. An output scanning chain is provided in a data line and a data value read from a register bank 14 is acquired on a data bus 24 when the debugging is operated. |
