| 摘要 |
PROBLEM TO BE SOLVED: To eliminate the waste of pull-in time to the locked state of a phase locked loop and to efficiently provide a phase locked state. SOLUTION: In this PLL(phase locked loop) circuit, phase control signals are obtained from a phase detector 12 and supplied to an operational amplifier 15 and frequency control signals are obtained from a frequency detector 13 and supplied to the operational amplifier 14. Then, the output of the operational amplifier 15 is supplied to the control terminal of a VCO(voltage controlled oscillator) 14 and a clock CK is obtained from the VCO 14, fed back to the phase detector 12 and the frequency detector 13 and turned to the object of phase comparison and frequency comparison with channel data.
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