| 摘要 |
PROBLEM TO BE SOLVED: To attain a high response of a loop without scarifying jitter performance on a screen by adopting a configuration such that a delay the same as a delay given to horizontal synchronizing pulse is also given to a horizontal drive pulse and it is fed to a horizontal output circuit to maintain a phase lock state of a PLL circuit. SOLUTION: The PLL circuit consists of a phase comparator 2, an LPF 3, a VCO 4, a horizontal drive pulse generating circuit 5, a variable delay circuit 6 and a horizontal output circuit 7. The phase comparator 2 detects a phase difference between a flyback pulse and a horizontal synchronous pulse delayed by a variable delay circuit 1 and a signal outputted from the LPF 3 controls an oscillated frequency from the VCO 4. The horizontal drive pulse generating circuit 5 receiving an output of the VCO 4 generates and outputs a horizontal drive pulse where the duty factor and the polarity of the pulse are controlled, the variable delay circuit 8 delays the pulse and the delayed pulse is given to the horizontal output circuit 7. When an image is distorted, a saw tooth wave obtained by a waveform generating circuit 8 is used to control the distortion. |
