发明名称 Vermittlungssystem und Verfahren zur Konstruktion davon
摘要 A switching system is disclosed in which a plurality of incoming highways are multiplexed in time division cells that have arrived are written into a buffer memory (105), the cells thus written are read in an appropriate order, separated in a multiplex way and distributed among a plurality of outgoing highways thereby to perform an exchange operation. An FIFO (First In First Out) buffer (103) stores an empty address of the buffer memory (105). The address in busy state is controlled in a manner corresponding to the outgoing highways. When a cell is written in the buffer memory (105), the empty address is taken out of the data output of the FIFO buffer. When the cell is read of the buffer memory (105) the address already read is returned to the data input of the FIFO buffer by an idle address chain (103-104-105-104-110-103).
申请公布号 DE3856370(T2) 申请公布日期 2000.06.21
申请号 DE19883856370T 申请日期 1988.07.14
申请人 HITACHI, LTD. 发明人 SAKURAI, YOSHITO;GOHARA, SHINOBU;OHTSUKI, KENICHI;MORI, MAKOTO;HORIKI, AKIRA;KATO, TAKAO;KUWAHARA, HIROSHI
分类号 H04L12/56;H04Q11/04;(IPC1-7):H04L12/54 主分类号 H04L12/56
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