| 摘要 |
When the use of a receiver the bus is not be acquired in delayed read or posted write, the length of a burst data transfer is limited by the capacity of the buffer in a bridge device. In order to solve this problem, waits are inserted in data output process via a sender bus in delayed read or posted write according to the condition of the receiver bus. As a result, input rate of data into the buffer in the bridge device is kept constant, and the use of the receiver bus can be acquired in the delayed read or the posted write. Data is simultaneously transferred into and from the buffer in the bridge device, so that the probability of burst data transfer with a long burst data transfer length is increased.
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