| 摘要 |
A method of forming a bottom gated TFT includes, a) providing a transistor gate relative to a substrate which projects outward thereof; b) providing a dielectric layer over the gate; c) providing a TFT layer of semiconductive material over the dielectric layer; the thin film transistor layer comprising a source area, a channel area, a drain area, and a drain offset area; d) providing a masking layer over the TFT layer; e) anisotropically etching the masking layer to define a masking sidewall spacer laterally adjacent the transistor gate over the drain offset area and leave the channel area outwardly exposed; f) with the masking sidewall spacer in place, implanting a conductivity enhancing impurity of a first type into the thin film channel area to provide a thin film channel region; and g) masking the channel area and the drain offset area while implanting conductivity enhancing impurity of a second type into the thin film source and drain areas to define thin film source and channel regions. Also contemplated is providing a fluorine containing layer over the polycrystalline thin film layer and over the sidewall spacer prior to the channel masking step, followed by annealing thereof at a temperature and for a time which in combination are effective to drive fluorine into the polycrystalline thin film layer and incorporate fluorine within grain boundaries in the polycrystalline thin film to passivate said grain boundaries. Top gated transistors are also contemplated, where the spacer is formed over a substrate elevation step.
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