PLL circuit and its automatic adjusting circuit

摘要

A 1/N programmable frequency divider for dividing the frequency of an output clock CLK1 from a VCO is connected between the VCO and a phase comparator in a PLL circuit. An adjusting circuit includes a counter for detecting a half-value of the frequency and for addressing a table ROM to make it read out a program data N and target value TV, a counter for detecting a half-value of the frequency of the output clock CLK from the 1/N programmable frequency divider, a digital comparator for comparing the count value of the counter and the target value TV and an up/down counter for incrementing or decrementing is count CFV in accordance with the comparison result, the count CFV being provided to the control input of the VCO.