发明名称
摘要 A bit line sensing circuit of a semiconductor memory device is disclosed which includes a pull-up control signal generator that enables the peak current to be small by supplying to the P sense amplifier a pull-up voltage of the low level in an initial sensing process. When the peak current is stabilized, the pull-up control signal generator then reduces the time required for raising the pull-up voltage by very quickly raising the voltage of the pull-up control signal. This results in the advantages that the peak current can be greatly reduced without slowing sensing speed, and voltage noise caused from peak currents can be eliminated.
申请公布号 JP3053562(B2) 申请公布日期 2000.06.19
申请号 JP19950331607 申请日期 1995.12.20
申请人 发明人
分类号 G11C11/409;G11C7/06;G11C7/22;G11C11/407;H01L21/8242;H01L27/108 主分类号 G11C11/409
代理机构 代理人
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