发明名称 |
FAILURE ANALYZING SYSTEM OF SEMICONDUCTOR MEMORY AND NAVIGATION METHOD OF SPECIMEN STAGE OF SURFACE OBSERVATION DEVICE |
摘要 |
PROBLEM TO BE SOLVED: To improve efficiency of failure analyzing work of a semiconductor memory by making a physical address of a bad cell and a layout information of a chip surface of a semiconductor memory a navigation information of a specimen stage and observing the surface of the bad cell. SOLUTION: A memory tester 1 detects a bad cell or a semiconductor memory which is an object of failure analysis and outputs the logic address of the bad cell to a logic address/physical address converting means 2. The address converting means 2 collects the logic address of the bad cell and coverts it to a physical address on a chip surface, refering to design data. In a surface observation device 4, the physical address of the bad cell and the layout information of the chip surface of the semiconductor memory in a layout information forming means 3 are made the navigation information of a specimen stage 5, and surface observation of the bad cell is performed.
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申请公布号 |
JP2000164659(A) |
申请公布日期 |
2000.06.16 |
申请号 |
JP19980336901 |
申请日期 |
1998.11.27 |
申请人 |
FUJITSU LTD |
发明人 |
ABE TAKAYUKI;TEGURI HIRONORI;HONJO ICHIRO;MIZUNO HIROHISA |
分类号 |
G01R31/28;H01L21/66;H01L27/10;(IPC1-7):H01L21/66 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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