| 摘要 |
PROBLEM TO BE SOLVED: To reduce the inter-wiring capacitance in an integrated circuit by connecting lower elements underlying a dielectric to down vias through conductors at an upper part level and connecting upper elements overlying the dielectric to up vias through conductors at a lower part level. SOLUTION: This integrated circuit has metal wirings, down vias 12 and up vias 13. The down via 12 has an extension 14 having the same width as that of the wiring 11a, 11b for electric connection between an element at a lower level n1 and a wiring 11b at an upper part level n2. One of the vias 13, similarly has a down extension 15 at the upper part level n2 for electric connection with a conductor 11a connected to the actual vias 13. Thus the inter-wiring capacitance in the integrated circuit can be reduced. |
