GROOVED DAMASCENE LINE FOR LOW-RESISTANCE WIRING OF INTEGRATED CIRCUIT

摘要

PROBLEM TO BE SOLVED: To achieve low capacitance and low resistance by simultaneously performing the pattern formation of a via and a grooved line in an interlayer dielectric, by simultaneously etching the via and the grooved line, and by simultaneously filling the via and the grooved line with metal. SOLUTION: On a substrate, desired linear features and vertical interconnection are formed (S700). A grooved line and a via are simultaneously etched (S701). A metallization layer is subjected pattern formation by lithography, and is etched by RIE or the like (S702). The via and the grooved line are filled by the same metallization process (S703). The filled via and the grooved line are finished by one-time common etching or polishing process so that a structure has a flat and uniform upper surface (S704). As a result, both of low-capacitance and low-resistance metallization can be formed.