ELECTROSTATIC DISCHARGE PROOF TRANSISTOR OF SEMICONDUCTOR CHIP AND LAYOUT THEREOF

摘要

PURPOSE: An electrostatic discharge proof transistor of semiconductor chip and a layout thereof are provided to minimize the layout size, and to prevent the electrostatic discharge from harming the semiconductor chip. CONSTITUTION: An electrostatic discharge proof transistor of semiconductor chip and a layout thereof include a plurality of input/output pads. Each of the plurality of input/output pads includes an electrostatic discharge proof transistor of diode topology, and an electrostatic discharge proof transistor with second type. The electrostatic discharge proof transistor are coupled between the input/output pads and the ground. The electrostatic discharge proof transistor of second type includes a plurality of power electrostatic discharge proof transistors. The electrostatic discharge proof transistor of second type are coupled in parallel with each other.