发明名称 |
DITHERING CIRCUIT AND METHOD |
摘要 |
PURPOSE: A dithering circuit and a method for the same are provided to implement a dithering matrix value, which is designated by a pixel address as a certain value in a dithering matrix, by using logic gates, and to implement the gates in a software manner. CONSTITUTION: In a dithering circuit for implementing an N-by-N dithering matrix, a plurality of XOR gates receive binary bits of a row and a column, and then perform an exclusive OR operation of the received binary bits. The row and column represent the pixel address of a certain location in the N-by-N dithering matrix. A pixel value of the N-by-N dithering matrix is comprised of the outputs from the XOR gates, and binary bit values of a column, which are inputted into the XOR gates. The values that represent a location in the N-by-N dithering matrix are obtained by the remainder of N.
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申请公布号 |
KR100258919(B1) |
申请公布日期 |
2000.06.15 |
申请号 |
KR19930022955 |
申请日期 |
1993.10.30 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
CHOI, BYONG-GYUN;UH, GIL-SOO;JIN, DAE-HYUN |
分类号 |
H04N1/409;G06F7/32;G06T5/00;H04N1/405;H04N1/41;(IPC1-7):G06F7/32 |
主分类号 |
H04N1/409 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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