ULTRA HIGH-SPEED SEMICONDUCTOR INTEGRATED CIRCUIT INTERCONNECT STRUCTURE AND FABRICATION METHOD USING FREE-SPACE DIELECTRIC

摘要

Ultra high-speed multi-level interconnect structure and fabrication process flows are disclosed for a semiconductor integrated circuit chip. The interconnect structure includes a plurality of conductive metallization levels (M1 - M5). Each of the metallization levels includes a plurality of conductive interconnect lines. A plurality of conductive plugs (via plugs 1 - via plugs 5) make electrical connections between various metallization levels as well as between the metallization levels and the semiconductor devices fabricated on the semiconductor substrate. The interconnect lines and plugs are at least partially surrounded by a free-space medium and are formed using an electrically conducting or semi-conducting disposable filler material that can be removed using a dry etch process. A top passivation overlayer hermetically seals the multi-level interconnect structure.