Short-term voltage spike filtering arrangement in digital integrated circuit

摘要

The arrangement includes a first OR gate (ORl) and a first AND gate (AND), at whose first inputs an input signal (sigin) is respectively supplied. A delay arrangement (D) with a predetermined time constant (t) is provided for delaying the input signal, whereby the output signal (indel) of the delay arrangement is respectively supplied to a second input of the first OR gate and that of the AND gate. A multiplexer circuit (MUX) is respectively provided for selectively switching the output signal (in1) of the first OR gate or the output signal (in0) of the AND gate to an output signal of the multiplexer circuit. The selection of the multiplexer circuit is preferably performed dependent on a selection signal (sel) which is taken from the output signal of the multiplexer circuit and is supplied to a control input of the multiplexer circuit.