发明名称 |
Rechner für die diskrete Cosinus-Transformation |
摘要 |
<p>Disclosed is an improved discrete cosine transform processor comprising an input unit for receiving image date to be processed, a storage unit for previously storing a result of a multiplication and accumulation calculation effected beforehand with respect to image input data and transform matrix components so that the same value is read from the same read line; a decoding unit for selecting the read line, in which each bit value of the image input data composed of a plurality of bits serves as a piece of address data; an accumulation unit for accumulating the data read from the storage unit and an output unit for outputting a result of the accumulation processing as output data. The storage unit uses the common data in common when effecting the multiplication and accumulation calculation, and, hence, a storage capacity is reduced, thereby making it possible to decrease a chip area. <IMAGE></p> |
申请公布号 |
DE69424377(D1) |
申请公布日期 |
2000.06.15 |
申请号 |
DE1994624377 |
申请日期 |
1994.11.30 |
申请人 |
KABUSHIKI KAISHA TOSHIBA, KAWASAKI |
发明人 |
KIM, LEE-SUP;NAGAMATSU, TETSU;SAKURAI, TAKAYASU |
分类号 |
H04N19/60;G06F17/14;G06T1/20;G06T9/00;H04N1/41;H04N19/42;H04N19/423;H04N19/426;H04N19/625;(IPC1-7):G06F17/14 |
主分类号 |
H04N19/60 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|