| 摘要 |
PURPOSE: A common microprocessor bus arbiter is provided to enable an access arbitration without requesting a use right of a CPU bus to be operated independently in a system adopting a master processor and a plurality of slave processors. CONSTITUTION: The device comprises a logic 1, a D-flip flop 1, a D-flip flop 2, an inverter, a logic 2, a logic 3 and a delayer. The logic 1 outputs a high signal only if a strobe B signal, input from a micro controller, is low and an output of the logic 2 is low. The D-flip flop 1 receives the output of the logic 1 and resets the output of the logic 2. The D-flip flop 2 receives the output of the logic 1, resets the output of the logic 2, and outputs the clock signal inverted with the signal of the D-flip flop 1. The logic 2 outputs a high signal only if a strobe A, input from the CPU is low and the output of the D-flip flop 1 and the D-flip flop 2 is low. The inverter inverts the output of the logic 2 and supplies an enable signal of a buffer. The logic 3 outputs a high signal only if the strobe B is low and the output of the D-flip flop 2 is low.
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